LVDS stands for: Low Voltage Differential Signaling. Revision 2.0 increases the speed to 5GT/s. The reduction in throughput is accounted for under the protocol section. The 8B/10B changes the data transfer numbers to 250MBps per lane, raw data. PCI Express supports 1x, 2x, 4x, 8x, 12x, 16x, and 32x bus widths 2.5Gigabits/second per Lane per Direction. A PCI Express link is comprised of these two unidirectional differential pairs each operating at 2.5Gbps to achieve a basic over all throughput of 5Gbps. This is a serial bus which uses two low-voltage differential LVDS pairs, at 2.5Gb/s in each direction. How ever the electrical and mechanical interface for PCI Express is not compatible with the PCI bus interface. PCI Express is the new serial bus addition to the PCI series of specifications. The Physical Layer resides with Layer 1, and the Data Link Layer resides with Layer 2 of the OSI protocol model. In addition to the Physical Layer, the PCI Express specification also covers the Transaction Layer and Data Link Layer. The PCI Express bus defines the Electrical, topology and protocol for the physical layer of a point to point serial interface over copper wire or optical fiber. ![]() A description of the new Serial PCI Bus "PCI Express".
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